A low dropout or LDO linear voltage regulator is an electronic circuit that is designed to provide a stable DC output voltage regardless of input voltage variations and load impedance. An LDO regulator is able to maintain output regulation even for a relatively small difference between the input voltage and the output voltage. For example, when regulating the voltage from a battery, an LDO regulator can maintain a steady output voltage for input voltages ranging from high battery voltages down to voltage levels just above the output voltage. A typical LDO regulator may use a field effect transistor (FET) as a current pass element, with the FET behaving as a resistor and dropping voltage across its terminals to maintain the desired output voltage. As the load current or input voltage changes, the gate to source voltage of the FET is adjusted by a control circuit to keep the output in regulation. The FET operates in the linear region as long as it has a minimum resistance, but if the control circuit causes the FET to operate below this minimum resistance, the FET enters the saturation region and the LDO is in dropout. Generally, the dropout voltage should be as low as possible for an LDO regulator.
Another important characteristic of an LDO regulator is its supply rejection, the ability to reject noise from the power supply. The supply rejection of a conventional LDO regulator depends on the loop gain of the regulator. Because the loop stability limits the available loop gain, it can be difficult to achieve high supply rejection at high frequency due to the limited loop gain. One technique to improve supply rejection is to include an RC filter made up of a resistor-capacitor network to filter supply noise at the input of the regulator. However, using an RC filter to increase supply rejection also results in a high dropout voltage. Another technique to improve supply rejection is to use cascaded NMOS and PMOS pass elements, with the gate voltage for the NMOS pass element being raised higher than the supply voltage by a charge pump. However, this technique increases circuit complexity and leads to high power consumption.
Yet another technique to improve supply rejection in an LDO regulator is to use a feedforward path to cancel ripple at the input from the power supply. Typically, in an LDO regulator a DC reference voltage is used to set the output voltage. In an LDO regulator with feedforward, a feedforward path is used in conjunction with the DC reference voltage to cancel input ripple. As illustrated in FIG. 1, the pass element 10 is controlled by the combination of a main error amplifier path 12 and a feedforward path 14. The main error amplifier path 12 compares the voltage at the output 16 with the DC reference voltage 20 to generate a feedback signal 22. The feedforward path 14 generates a feedforward signal 24 using additional amplifiers (e.g., 26) with resistors (e.g., 30 and 32) and capacitors (e.g., 34). The feedforward signal 24 contains a representation of the ripple noise from the power supply 36 which is combined in amplifier 40 with the feedback signal 22 to achieve high supply rejection.
However, the feedforward signal 24 generated using amplifiers (e.g., 26) with resistors (e.g., 30 and 32) and capacitors (e.g., 34) is susceptible to process-voltage-temperature (PVT) variations because of the large variations of RC values in the feedforward path 14. In addition, when the gain of the main amplifier 40 is modified, the feedforward path 14 should be adjusted accordingly, adding complexity to the LDO regulator 42.